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3 MOTION DEDICATED PLC INSTRUCTION
CPU dedicated instruction transmission area shown in table below is
allocated as initial setting.
Table 3.1 Number of CPU dedicated instruction transmission area
Number of Multiple CPU modules
Number of CPU dedicated instruction transmission area for
each target CPU
2 47 blocks
3 23 blocks
4 15 blocks
As shown in Table 3.2, each Motion dedicated PLC instruction uses a
certain number of blocks in the CPU dedicated instruction transmission area
until the "complete device" turns on by the PLC CPU after instruction
execution.
Table 3.2 Number of blocks used for Motion dedicated PLC instruction
Instructions Number of blocks used
D(P).SFCS 1
D(P).SVST 1
D(P).CHGA 1
D(P).CHGAS
QDS
Ver.!
1
D(P).CHGV 1
D(P).CHGVS
QDS
Ver.!
1
D(P).CHGT 1
D(P).CHGT2
QDS
1
D(P).DDWR
2
(Note)
D(P).DDRD
2
(Note)
D(P).GINT 1
(Note): When the number of transmitted data is 4 words or less, number of blocks used is 1.
[Operation example]
Below is an example when 12 D(P).SVST instructions and 12 D(P).DDWR
instructions (5 word or more each) are executed simultaneously.
The number of blocks used is as follows;
12 D(P).SVST instructions
1 block each +
12 D(P).DDWR instructions
2 blocks each
= 36 (Total blocks used)
Ver.!
: Refer to Section 1.3 for the software version that supports this function.
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