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Neoway N715-EA - SD Card Interface Reference Design

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N715-EA Hardware User Guide
Chapter 5 Application Interfaces
Copyright © Neoway Technology Co., Ltd. All rights reserved.
49
Figure 5-22 Reference design of the SD card interface
SDIO1_DATA0
SDIO1_DATA1
SDIO1_DATA2
SDIO1_DATA3
SDIO1_CMD
SDIO1_CLK
SDIO1_DET
N715-EA Module
SD Card Slot
DATA_0
DATA_1
DATA_2
DATA_3
CMD
CLK
DET
VDD_1P8
R1
R2
R3
R4
R5
R6
R7
R8 R9 R10 R11 R12
R13
C1
C2
C3
C4 C5 C6 C7
0Ω
10K 47K
NC NC NC NC
NC NC
NC
10K
10K 10K 10K
D1 D2 D3 D4 D5 D6 D7
VSS
VDD
C8
47uF
C9
33pF
D8
GND
SD_VDD
0Ω
0Ω
0Ω
0Ω
0Ω
1KΩ
VDD_SDCPULL
Schematic Design Guidelines
VDD_SDCPULL is a 1.8 V/3.0 V dual-voltage power supply; configure it according to the SD
card voltage type. It outputs a maximum current of 50 mA and is only used for SD pull-up. Do not
use it for any other purpose.
SD_VDD is used to drive SD card peripherals
N715-EA supports SD card detection, which is triggered by a 1.8 V interrupt pin. The SD
detection circuit works by checking the voltage-level across the USIM_DET pin before and after
a SD card is inserted. In the reference circuit, Figure 5-22, SD_DET is at a high-level voltage
(with external pull-up to VDD_1P8) before a SD card is inserted and is grounded after a SD card
is inserted. The low-level means SD card detected while the high-level means no SD card
detected.
PCB Design Guidelines
Ensure that the power supply trace width is not less than 0.6 mm.
Control the trace lengths of each SDIO signal. The DATA traces should be matched in length to
within 0.5 mm, and the CMD, CLK and DATA traces should be matched in length to within 0.5
mm.
Spacing between DATA traces should be larger than 2 times trace width.
Control the impedance for each SDIO trace to 50 Ω.
5.3.6 PCM
Signal
Pin
I/O
Function description
Remarks
PCM_SYNC
58
DI
PCM data frame sync
-
PCM_DIN
59
DI
PCM data input
-

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