Neoway N715-EA - PCM Interface Overview and Guidelines

N715-EA Hardware User Guide
Chapter 5 Application Interfaces
Copyright © Neoway Technology Co., Ltd. All rights reserved.
50
PCM_DOUT
60
DO
PCM data output
-
PCM_CLK
61
DO
PCM clock
-
N715-EA provides one 1.8 V PCM interface. The following figure shows the reference design of the
PCM interface.
Figure 5-23 PCM reference design
N715-EA Module
PCM_SCLK
PCM_SYNC
PCM_DIN
PCM_DOUT
PCM_SCLK
PCM_SYNC
PCM_DOUT
PCM_IN
Schematic Design Guidelines
If the levels of N715-EA and Codec do not match, add a voltage-level translation circuit as required by
referring to the description of voltage-level translation circuit in section 5.3.2 .
PCB Design Guidelines:
⚫
Reduce the cross routing between the PCM signal cable and other cables. If cross routing
cannot be avoided, keep this signal cable perpendicular to other cables to reduce coupling.
⚫
Keep the PCM signal cable away from areas where static electricity may be introduced.
⚫
PCM_SCLK should be ground shielded. It is also recommended that other signal cables be
shielded with surrounded ground.
5.3.7 SPI
Signal
Pin
I/O
Function description
Remarks
SPI_CLK
1
DO
Clock signal
Supporting only master
mode.
Leave this pin open if
unused.
SPI_MISO
2
DI
Output of the slave device and input of the
master device
SPI_MOSI
3
DO
Input of the slave device and output of the
master device
SPI_CS_N
4
DO
Chip select signal of the slave device