Panasonic AJ-SD93P/E - Ieee1394 Module (F3 Sub) Block Diagram

IEEE1394 MODULE (F3 SUB) BLOCK DIAGRAM
BLK-7
PHY
SDRAM
1.8MHz
CLK
GEN.
RESET
IC10501 (5)
IC10401 (4)
IC10601 (6)
25MHz
CLK GEN.
X10201, IC10201 (2)
TPB-, TPB+ 1, 2
P10301
P10302
X10401 (4)
8 PHY DATA BUS
2 PYH CONTROL BUS
CLK
RAM ADRS 13
RAM DATA 16
RAM CONTROLL
IC10707 (4)
RESET
GEN. &
GATE
IC10705,
10707 (7)
6-12B,
14-21B
TPA-, TPA+ 4, 5
TPB-, TPB+ 1, 2
TPA-, TPA+ 4, 5
UPDAT (0-15)
5-12A,
14-21A
UPADR (1-15)
40A-48A
DVPBDAT (0-7) 41B-48B
DVRECDAT (0-7)
CFNRESET 34A
NPOWERDOWN
NUPCS, NUPRD,
NUPWAIT, NUPBHW,
NUPBLW, BCLK,
NUPINT
2A, 5B,
22A/B,
23A/B,
24A/B
DVPBFRM,
DVPBSSP,
DVREFFRM,
DVRECFRM,
DVRECSSP
37-39A
38,39B
CFCLK 33B
CF DATA 32B
FPGA
DUEL
P10101
P10101
P10101
P1701
P1701
P1701
FROM/TO (F3)
DPROC
BOARD
IEEE1394
CONNECTOR
NRESET 2B
P10101
P1701