Renesas RL78/G13 - Page 158

RL78/G13 CHAPTER 3 CPU ARCHITECTURE
R01UH0146EJ0100 Rev.1.00 139
Sep 22, 2011
Table 3-5. SFR List (3/5)
Manipulable Bit Range Address Special Function Register (SFR) Name Symbol R/W
1-bit 8-bit 16-bit
After Reset
FFF6AH
FFF6BH
Timer data register 05 TDR05 R/W
− − √
0000H
FFF6CH
FFF6DH
Timer data register 06 TDR06 R/W
− − √
0000H
FFF6EH
FFF6FH
Timer data register 07 TDR07 R/W
− − √
0000H
FFF70H
FFF71H
Timer data register 10 TDR10 R/W
− − √
0000H
FFF72H TDR11L
− √
00H
FFF73H
Timer data register 11
TDR11H
TDR11 R/W
− √
√
00H
FFF74H
FFF75H
Timer data register 12 TDR12 R/W
− − √
0000H
FFF76H TDR13L
− √
00H
FFF77H
Timer data register 13
TDR13H
TDR13 R/W
− √
√
00H
FFF78H
FFF79H
Timer data register 14 TDR14 R/W
− − √
0000H
FFF7AH
FFF7BH
Timer data register 15 TDR15 R/W
− − √
0000H
FFF7CH
FFF7DH
Timer data register 16 TDR16 R/W
− − √
0000H
FFF7EH
FFF7FH
Timer data register 17 TDR17 R/W
− − √
0000H
FFF90H
FFF91H
Interval timer control register ITMC R/W
− − √
0FFFH
FFF92H Second count register SEC R/W
− √ −
00H
FFF93H Minute count register MIN R/W
− √ −
00H
FFF94H Hour count register HOUR R/W
− √ −
12H
Note
FFF95H Week count register WEEK R/W
− √ −
00H
FFF96H Day count register DAY R/W
− √ −
01H
FFF97H Month count register MONTH R/W
− √ −
01H
FFF98H Year count register YEAR R/W
− √ −
00H
FFF99H Watch error correction register SUBCUD R/W
− √ −
00H
FFF9AH Alarm minute register ALARMWM R/W
− √ −
00H
FFF9BH Alarm hour register ALARMWH R/W
− √ −
12H
FFF9CH Alarm week register ALARMWW R/W
− √ −
00H
FFF9DH Real-time clock control register
0
RTCC0 R/W
√ √ −
00H
FFF9EH Real-time clock control register
1
RTCC1 R/W
√ √ −
00H
Note The value of this register is 00H if the AMPM bit (bit 3 of real-time clock control register 0 (RTCC0)) is set to 1 after
reset.