RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 689
Sep 22, 2011
(2) Processing flow
Figure 12-110. Timing Chart of Data Transmission
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6
SSmn
SEmn
SOEmn
SDRmn
SCLr output
SDAr output
SDAr input
Shift
register mn
INTIICr
TSFmn
D5 D4 D3 D2 D1 D0
ACK
Shift operation
“L”
“H”
“H”
Transmit data 1
Figure 12-111. Flowchart of Data Transmission
Starting data transmission
Data transmission
completed
Transfer end interrupt
enerated?
No
Yes
Writing data to SIOr
(SDRmn[7:0])
No
Yes
ACK reception error
top con
t
on generat
on
Data transfer completed?
Yes
No
Address field
transmission completed
Parity error (ACK error) flag
PEFmn = 1 ?