Renesas RL78/G13 - Page 826

RL78/G13 CHAPTER 15 DMA CONTROLLER
R01UH0146EJ0100 Rev.1.00 807
Sep 22, 2011
Figure 15-4. Format of DMA Mode Control Register n (DMCn) (3/3)
Address: F020AH (DMC2), F020BH (DMC3) After reset: 00H R/W
Symbol <7> <6> <5> <4> 3 2 1 0
DMCn STGn DRSn DSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0
(When n = 2 or 3)
Selection of DMA start source
Note
IFCn
3
IFCn
2
IFCn
1
IFCn
0
Trigger signal Trigger contents
0 0 0 0
−
Disables DMA transfer by interrupt.
(Only software trigger is enabled.)
0 0 0 1 INTAD A/D conversion end interrupt
0 0 1 0 INTTM10 End of timer channel 10 count or capture
end interrupt
0 0 1 1 INTTM11 End of timer channel 11 count or capture
end interrupt
0 1 0 0 INTTM12 End of timer channel 12 count or capture
end interrupt
0 1 0 1 INTTM13 End of timer channel 13 count or capture
end interrupt
0 1 1 0 INTST3/INTCSI30
UART3 transmission transfer end or
buffer empty interrupt/CSI30 transfer end
or buffer empty interrupt
0 1 1 1 INTSR3/INTCSI31
UART3 reception transfer end
interrupt/CSI31 transfer end or buffer
empty interrupt
1 0 0 0 INTST1/INTCSI10
UART1 transmission transfer end or
buffer empty interrupt/CSI10 transfer end
or buffer empty interrupt
1 0 0 1 INTSR1/INTCSI11
UART1 reception transfer end
interrupt/CSI11 transfer end or buffer
empty interrupt
1 0 1 0 INTST2/INTCSI20
UART2 transmission transfer end or
buffer empty interrupt/CSI20 transfer end
or buffer empty interrupt
1 0 1 1 INTSR2/INTCSI21
UART2 reception transfer end
interrupt/CSI21 transfer end or buffer
empty interrupt
Other than above Setting prohibited
Note The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 bits values.
Remark n: DMA channel number (n = 2, 3)