RL78/G13 CHAPTER 15 DMA CONTROLLER
R01UH0146EJ0100 Rev.1.00 819
Sep 22, 2011
DWAIT0 = 1
DWAIT1 = 1
DST0 = 0
DST1 = 0
DEN0 = 0
DEN1 = 0
DWAIT0 = 0
DWAIT1 = 0
DWAIT0 = 1
DWAIT1 = 1
DSTn = 0
DENn = 0
DWAIT0 = 0
DWAIT1 = 0
Figure 15-11. Forced Termination of DMA Transfer (2/2)
Example 3
• Procedure for forcibly terminating the DMA • Procedure for forcibly terminating the DMA
transfer for one channel if both channels are used transfer for both channels if both channels are used
Caution In example 3, the system is not required to wait two clock cycles after the DWAITn bit is set to 1. In
addition, the system does not have to wait two clock cycles after clearing the DSTn bit to 0,
because more than two clock cycles elapse from when the DSTn bit is cleared to 0 to when the
DENn bit is cleared to 0.
Remarks 1. n: DMA channel number (n = 0, 1)
2. 1 clock: 1/f
CLK (fCLK: CPU clock)
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