R&S PR100 User Manual
Bit
No.
Meaning
5 Command Error
This bit is set if an undefined and syntactically incorrect command is
received. An error message with a number between -100 and -199
denoting the error in greater detail is entered into the error queue
(see Section 9.3).
7 Power On (supply voltage on)
This bit is set when the device is switched on.
9.2.1.4 STATus:OPERation register
In the CONDition section, this register contains information about the type of
actions currently being executed by the device. In the EVENt section, it also
contains information about the type of actions having been xecuted since the
last reading. It can be read using the commands
"STATus:OPERation:CONDition?" or
"STATus:OPERation[:EVENt]?".
Table 4: Bit allocation of STATus:OPERation register
Bit
No.
Meaning
3 SWEeping
This bit is set when the sum bit of STATus:OPERation:SWEeping bits
is set
4 MEASuring
This bit is set for the duration of a measurement
8 TESTing
This bit is set when a self-test is running
9.2.1.5 STATus:OPERation:SWEeping register
This register contains more detailed information on the operating state of the
device. The device is either set to normal receive mode (Fixed Frequency
Mode FFM) or to one of several scan modes (FSCAN, MSCAN, PSCAN).
The status is determined by using the command SENSe:FREQuency:MODE.
The CW|FIXed status is set by clearing bits 3 to 7 from the
STATus:OPERation:SWEeping register.
Table 5: Bit allocation of STATus:OPERation:SWEeping register
Bit
No.
Meaning
0 Hold
This bit is set if an FSCAN or MSCAN was interrupted due to the
fulfillment of a hold criterion.
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