B.27 MSP-TS430RGC64C
The MSP-TS430RGC64C target board has been designed with the option to operate with the target device
DVIO input voltage supplied via header J6 (see Figure B-54). This development platform does not supply the
1.8-V DVIO rail on board and it MUST be provided by external power supply for proper device operation. For
correct JTAG connection, programming, and debug operation, it is important to follow this procedure:
1. Make sure that the VCC and DVIO voltage supplies are OFF and that the power rails are fully discharged to
0 V.
2. Enable the 1.8-V external DVIO power supply.
3. Enable the 1.8-V to 3.6-V VCC power supply (alternatively, this supply can be provided from the MSP-
FET430UIF JTAG debugger interface).
4. Connect the MSP-FET430UIF JTAG connector to the target board.
5. Start the debug session using IAR or CCS IDE.
For more information on debugging the MSP430F522x and MSP430F525x, see the device-specific data sheets
(MSP430F522x and MSP430F525x) and Designing with MSP430F522x and MSP430F521x Devices.
For debugging of devices (MSP430F524x and MSP430F523x) without use of the DVIO power domain, short JP4
with the jumper.
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Hardware
SLAU278AG – MAY 2009 – REVISED DECEMBER 2020
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