2 3 4 Meaning
o 0
I/o
address not
recognized,
HIO not
ac-
cepted,
and no status i nformati on returned
to
general
registers.
o
No
I/O
address
recognized
and HIO
aborted
because
an
error
detected
when
the
lOP
at-
tempted
to
read
and
transfer
the
HIO
param-
eters
(device/device
controller
address
and
R field information) from
the
BP
to the
lOP.
No
status information returned
to
general
registers.
If CC4 = 1,
the
MIOP
is
in
the
test
mode and
the
meaning
of
the
condition
code
during
an
HIO is:
2 3 4 Meaning
o 0 0 Unit is performing
an
Order
Out
operation.
o o
o 0
o
o
Unit is performing
an
Order
In
operation.
Unit is performing a Data
Out
operation.
Processor
Interface
detected
parity error on
returned status
and/or
condition
code.
The
result of the
HIO is indeterminate.
Unit is performing a Data In operation.
BCF
detected
while
unit
performing a Data
In operati on.
RF~FT
TNPIIT
/()IITPIIT
0N~~d
i~de~
'~Iig~~e~i,
t privileged)
RESET
INPUT/OUTPUT causes the
selected
lOP
to
generate
an
I/O
reset signal
to
all
devices
attached
to
it.
In
addi-
tion to the operation
code
X'4F',
bits 15, 16, and 17 must
be
coded
as
001,
respectively.
An
RIO
instruction resets
the
selected
unit
in
the
same
manner as
ZCRIO on
the
operator's
control console. How-
ever,
unlike
the
control command,
the
RIO
instruction
resets only the addressed
unit
and may be
controlled
by
the
executing
program. Since
the
BP
may be addressed as
an
lOP,
it
wi
II
accept
an
RIO
instruction
that
causes
the
BP
to reset itself in the same manner as
ZCRBP.
(Note
that
this procedure
is
not normal
practice.)
C luster addresses (CA),
bit
positions
18-20,
may
have
values
of
XIOI_X?I.
Cluster addresses X
'
0'-X
'
6
1
may be assigned
to
any
cluster containing processors
(i
.e.,
BP,
MIOP,
and/
or RMP).
In
a monoprocessor system,
cluster
address
XIO
I
is
assi.gned to the c luster
containing
the basic processor
(BP). Cluster address
X?I
is
assigned only to the
cluster
containing a system processor.
If
CA equals
X?I
I the
UA
field
is
reserved. Unit addresses (UA),
bit
positions
21-23,
may have values
of
XIOI_X?I. Unit addresses
are
required
only
if
the
cluster
address
is
X
'
0'_X
'
6
1
,
(i.e.,
cluster
contains
either
a
BP,
MIOP,
and/or-RMP). Unit addresses
X
101_X
15
1
may be assigned to processors within the
cluster.
Unit address X
'
5
1
in
cluster
XIO
I
is
reserved for the
BP.
Unit
address
X
'
6
1
is
assigned always to the
MI
and
unit
address
X?I
is
assigned always to the
PI
for
all
clusters.
Status information is returned only in
the
condition
code
bits. The R field is not used.
Affected:
CC1, CC2, CC3
Condition
code
settings
are
as shown below:
2 3 4 Meaning
o 0 0 -
I/O
address
recognized.
o -
I/O
address not
recognized.
POLP
POLL
PROCESSOR
(Word
index
alignment,
t privileged)
POLL
PROCESSOR causes
the
addressed
unit
to
return unit
fau
I t status in
bi
ts 16-31 of reg i ster Rtt.
Th
i s status i
nfor-
mation is
unit
dependent
(see Appendix
C,
Table
C-1).
In
addition
to
the
operation
code
of X
'
4F' I bits 15, 16,
and
17 must be
coded
as
010,
respectively.
Affected: (R),
CC1,
CC2,
CC~
Condition Code settings
are
as shown below:
2 3 4 Result of
POLP
o 0 0 - Processor
fault
interrupt not pending.
o 0 - Processor
fault
interrupt pending.
o
~
Unit address not
recognized.
POLR
POLL
AND
RESET
PROCESSOR
(Word index
alignment,
t privileged)
POLL
AND
RESET
PROCESSOR causes
the
selected
unit
to
return unit
fault
status in bits 16
to
31
of register
Rtt
and
resets
the
unit's
fault
status register. This status informa-
tion
is
unit
dependent
(see Appendix
C,
Table
C-1).
tSee
footnote
to
HIO instruction.
tt
This
fault
status
is
duplicated
in bits 0
to
15
of register
R.
Input/Output
Instru ctions 139
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