Xilinx ChipScope Pro User Manual

ChipScope Pro Software and Cores User Guide www.xilinx.com 221
UG029 (v14.3) October 16, 2012
ChipScope Pro Analyzer Core Troubleshooting
5. Have the core constraints been
applied correctly?
If NO or NOT SURE: Check that a PERIOD constraint has been added to
the clock used as the CLK input to the ILA core. If there is no constraint on
this net in the ISE project, the timing constraints are not applied correctly
and might result in the cores not being recognized. Also check that the
NCF file associated with the core was applied. If the core netlist file
(*.ngc/ngo) was moved during implementation the associated constraint
file (*.ncf) might not have been moved accordingly.
If YES: Go to Issue #6.
6. Is the JTAG TCK clock running too
fast?
If YES or NOT SURE: Reduce the speed of the cable using the JTAG Chain
> Xilinx Platform USB Cable > Speed option to slow the frequency of the
TCK pin to the lowest setting.
If NO: Open a case with Xilinx Technical Support including the following
information:
• cs_analyzer.log
• Archived ISE project including inserter project (<filename>.cdc)
Table A-9: Troubleshooting ILA Core Triggering Issues (Cont’d)
Issue(s) Solution(s) or Work-Around(s)

Xilinx ChipScope Pro Specifications

General

Brand	Xilinx
Model	ChipScope Pro
Category	Computer Hardware
Language	English