Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 133
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
The extended address load and store instructions are privileged when the MMU is
enabled, unless they are allowed by setting the parameter
C_MMU_PRIVILEGED_INSTR
appropriately. If allowed, the instructions bypass the MMU translation treating the
extended address as a physical address.
• The GNU compiler does not handle 64-bit address pointers, which means that unless
PAE is enabled the only way to access an extended address is using the specific
extended addressing instructions, available as macros.
The following C code exemplifies how an extended address can be used to access data:
#include “xil_types.h”
#include “mb_interface.h”
int main()
{
u64 Addr = 0x000000FF00000000LL; /* Extended address */
u32 Word;
u8 Byte;
Word = lwea(Addr); /* Load word from extended address */
swea(Addr, Word); /* Store word to extended address */
Byte = lbuea(Addr); /* Load byte from extended address */
sbea(Addr, Byte); /* Store byte to extended address */
}
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module