Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 85
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Data Cache
Overview
The MicroBlaze processor can be used with an optional data cache for improved
performance. The cached memory range must not include addresses in the LMB address
range. The data cache has the following features:
• Direct mapped (1-way associative)
•Write-through or Write-back
• User selectable cacheable memory address range
• Configurable cache size and tag size
• Caching over AXI4 interface (
M_AXI_DC)
• Option to use 4, 8 or 16 word cache-lines
• Cache on and off controlled using a bit in the MSR
• Optional WDC instruction to invalidate or flush data cache lines
• Optional victim cache with write-back to improve performance by saving evicted cache
lines
• Optional parity protection for write-through cache that invalidates cache lines if a Block
RAM bit error is detected
• Optional data width selection to either use 32 bits, an entire cache line, or 512 bits
General Data Cache Functionality
When the data cache is used, the memory address space is split into two segments: a
cacheable segment and a non-cacheable segment. The cacheable area is determined by
two parameters:
C_DCACHE_BASEADDR and C_DCACHE_HIGHADDR. All addresses within this
range correspond to the cacheable address space. All other addresses are non-cacheable.
The cacheable segment size must be 2
N
, where N is a positive integer. The range specified
by
C_DCACHE_BASEADDR and C_DCACHE_HIGHADDR must comprise a complete power-of-two
range, such that range = 2
N
and the N least significant bits of C_DCACHE_BASEADDR must be
zero.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module