Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 55
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Memory Architecture
MicroBlaze is implemented with a Harvard memory architecture; instruction and data
accesses are done in separate address spaces.
The instruction address space has a 32-bit virtual address range (that is, handles up to 4GB
of instructions), and can be extended up to a 64-bit physical address range when using the
MMU in virtual mode.
The data address space has a default 32-bit range, and can be extended up to a 64-bit
range (that is, handles from 4GB to 16EB of data). The instruction and data memory ranges
can be made to overlap by mapping them both to the same physical memory. The latter is
necessary for software debugging.
Both instruction and data interfaces of MicroBlaze are default 32 bits wide and use big
endian or little endian, bit-reversed format, depending on the selected endianness.
MicroBlaze supports word, halfword, and byte accesses to data memory.
Big endian format is only supported when using the MMU in virtual or protected mode
(
C_USE_MMU > 1) or when reorder instructions are enabled (C_USE_REORDER_INSTR = 1).
Data accesses must be aligned (word accesses must be on word boundaries, halfword on
halfword boundaries), unless the processor is configured to support unaligned exceptions.
All instruction accesses must be word aligned.
MicroBlaze prefetches instructions to improve performance, using the instruction prefetch
buffer and (if enabled) instruction cache streams. To avoid attempts to prefetch instructions
beyond the end of physical memory, which might cause an instruction bus error or a
processor stall, instructions must not be located too close to the end of physical memory.
The instruction prefetch buffer requires 16 bytes margin, and using instruction cache
streams adds two additional cache lines (32, 64 or 128 bytes).
MicroBlaze does not separate data accesses to I/O and memory (it uses memory-mapped
I/O). The processor has up to three interfaces for memory accesses:
• Local Memory Bus (LMB)
• Advanced eXtensible Interface (AXI4) for peripheral access
• Advanced eXtensible Interface (AXI4) or AXI Coherency Extension (ACE) for cache
access
The LMB memory address range must not overlap with AXI4 ranges.
The C_ENDIANNESS parameter is always set to little endian.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module