Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 194
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5
MicroBlaze Instruction Set Architecture
Introduction
This chapter provides a detailed guide to the Instruction Set Architecture of the MicroBlaze™
processor.
Notation
The symbols used throughout this chapter are defined in the following table.
Table 5-1: Symbol Notation
Symbol Meaning
+
Add
-
Subtract
×
Multiply
/
Divide
∧
Bitwise logical AND
∨
Bitwise logical OR
⊕
Bitwise logical XOR
x
Bitwise logical complement of x
←
Assignment
>>
Right shift
<<
Left shift
rx
Register x
x[i]
Bit i in register x
x[i:j]
Bits i through j in register x
=
Equal comparison
≠
Not equal comparison
>
Greater than comparison
>=
Greater than or equal comparison
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module