Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 189
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 4: MicroBlaze Application Binary Interface
Stack Convention
The stack conventions used by MicroBlaze are detailed in Table 4-3.
The shaded area in Table 4-3 denotes a part of the stack frame for a caller function, while
the unshaded area indicates the callee frame function. The ABI conventions of the stack
frame define the protocol for passing parameters, preserving non-volatile register values,
and allocating space for the local variables in a function.
Functions that contain calls to other subroutines are called as non-leaf functions. These
non-leaf functions have to create a new stack frame area for its own use. When the program
starts executing, the stack pointer has the maximum value. As functions are called, the stack
pointer is decremented by the number of words required by every function for its stack
frame. The stack pointer of a caller function always has a higher value as compared to the
callee function.
Table 4-3: Stack Convention
Consider an example where Func1 calls Func2, which in turn calls Func3. The stack
representation at different instances is depicted in
Table 4-1. After the call from Func 1 to
Func 2, the value of the stack pointer (SP) is decremented. This value of SP is again
decremented to accommodate the stack frame for Func3. On return from Func 3 the value
of the stack pointer is increased to its original value in the function, Func 2.
High Address
Function Parameters for called sub-routine (Arg n .. Arg1)
(Optional: Maximum number of arguments required for any
called procedure from the current procedure).
Old Stack
Pointer
Link Register (R15)
Callee Saved Register (R31....R19)
(Optional: Only those registers which are used by the
current procedure are saved)
Local Variables for Current Procedure
(Optional: Present only if Locals defined in the procedure)
Functional Parameters (Arg n .. Arg 1)
(Optional: Maximum number of arguments required for any
called procedure from the current procedure)
New Stack
Pointer
Link Register
Low Address
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module