Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 188
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 4: MicroBlaze Application Binary Interface
The architecture for MicroBlaze defines 32 general purpose registers (GPRs). These registers
are classified as volatile, non-volatile, and dedicated.
• The volatile registers (also known as caller-save) are used as temporaries and do not
retain values across the function calls. Registers R3 through R12 are volatile, of which
R3 and R4 are used for returning values to the caller function, if any. Registers R5
through R10 are used for passing parameters between subroutines.
• Registers R19 through R31 retain their contents across function calls and are hence
termed as non-volatile registers (a.k.a callee-save). The callee function is expected to
save those non-volatile registers, which are being used. These are typically saved to the
stack during the prologue and then reloaded during the epilogue.
• Certain registers are used as dedicated registers and programmers are not expected to
use them for any other purpose.
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Registers R14 through R17 are used for storing the return address from interrupts,
sub-routines, traps, and exceptions in that order. Subroutines are called using the
branch and link instruction, which saves the current Program Counter (PC) onto
register R15.
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Small data area pointers are used for accessing certain memory locations with 16-
bit immediate value. These areas are discussed in the memory model section of this
document. The read only small data area (SDA) anchor R2 (Read-Only) is used to
access the constants such as literals. The other SDA anchor R13 (Read-Write) is used
for accessing the values in the small data read-write section.
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Register R1 stores the value of the stack pointer and is updated on entry and exit
from functions.
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Register R18 is used as a temporary register for assembler operations.
• MicroBlaze includes special purpose registers such as:
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program counter (rpc)
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machine status register (rmsr)
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exception status register (resr)
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exception address register (rear)
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floating-point status register (rfsr), branch target register (rbtr)
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exception data register (redr)
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memory management registers (rpid, rzpr, rtlblo, rtlbhi, rtlbx, rtlbsx)
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processor version registers (0-12)
These registers are not mapped directly to the register file; and hence, the usage of these
registers is different from the general purpose registers. The value of a special purpose
registers can be transferred to or from a general purpose register by using mts and mfs
instructions respectively.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module