Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 196
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
Formats
MicroBlaze uses two instruction formats: Type A and Type B.
Type A
Type A is used for register-register instructions. It contains the opcode, one destination and two
source registers.
Type B
Type B is used for register-immediate instructions. It contains the opcode, one destination and one
source registers, and a source 16-bit immediate value.
Instructions
This section provides descriptions of MicroBlaze instructions. Instructions are listed in alphabetical
order. For each instruction Xilinx provides the mnemonic, encoding, a description, pseudocode of its
semantics, and a list of registers that it modifies.
Opcode Destination Reg Source Reg A Source Reg B 0 0 0 0 0 0 0 0 0 0 0
06
11 16 21
31
Opcode Destination Reg Source Reg A Immediate Value
06
11 16
31
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module