Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 135
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3
MicroBlaze Signal Interface Description
Introduction
This chapter describes the types of signal interfaces that can be used to connect a
MicroBlaze™ processor.
Overview
The MicroBlaze core is organized as a Harvard architecture with separate bus interface units
for data and instruction accesses. The following two memory interfaces are supported:
Local Memory Bus (LMB), and the AMBA® AXI4 interface (AXI4) and ACE interface (ACE).
The LMB provides single-cycle access to on-chip dual-port block RAM. The AXI4 interfaces
provide a connection to both on-chip and off-chip peripherals and memory. The ACE
interfaces provide cache coherent connections to memory.
MicroBlaze also supports up to 16 AXI4-Stream interface ports, each with one master and
one slave interface.
Features
MicroBlaze can be configured with the following bus interfaces:
• The AMBA AXI4 Interface for peripheral interfaces, and the AMBA AXI4 or AXI
Coherency Extension (ACE) Interface for cache interfaces (see Arm® AMBA® AXI and
ACE Protocol Specification, Arm IHI 0022E [Ref 15]).
• LMB provides a simple synchronous protocol for efficient block RAM transfers
• AXI4-Stream provides a fast non-arbitrated streaming communication mechanism
• Debug interface for use with the Microprocessor Debug Module (MDM) core
• Trace interface for performance analysis
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module