Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 129
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Coherency
MicroBlaze supports cache coherency, as well as invalidation of caches and translation look-
aside buffers, using the AXI Coherency Extension (ACE) defined in AMBA® AXI and ACE
Protocol Specification (
Arm IHI 0022E) [Ref 15]. The coherency support is enabled when the
parameter C_INTERCONNECT is set to 3 (ACE).
Using ACE ensures coherency between the caches of all MicroBlaze processors in the
coherency domain. The peripheral ports (
AXI_IP, AXI_DP) and local memory (ILMB, DLMB)
are outside the coherency domain.
Coherency is not supported with write-back data cache, wide cache interfaces (more than
32-bit data), instruction cache streams, instruction cache victims or when area optimization
is enabled. In addition both
C_ICACHE_ALWAYS_USED and C_DCACHE_ALWAYS_USED must be
set to 1.
Invalidation
The coherency hardware handles invalidation in the following cases:
• Data Cache invalidation: When a MicroBlaze core in the coherency domain invalidates a
data cache line with an external cache invalidation instruction (
WDC.EXT.CLEAR or
WDC.EXT.FLUSH), hardware messages ensure that all other cores in the coherency
domain will do the same. The physical address is always used.
• Instruction Cache invalidation: When a MicroBlaze core in the coherency domain
invalidates an instruction cache line, hardware messages ensure that all other cores in
the coherency domain will do the same. When the MMU is in virtual mode the virtual
address is used, otherwise the physical address is used.
• MMU TLB invalidation: When a MicroBlaze core in the coherency domain invalidates an
entry in the UTLB (that is writes TLBHI with a zero Valid flag), hardware messages
ensure that all other cores in the coherency domain will invalidate all entries in their
unified TLBs having a TAG matching the invalidated virtual address, as well as empty
their shadow TLBs.
The TID is not taken into account when matching the entries, which can result in
invalidation of entries belonging to other processes. Subsequent accesses to these
entries will generate TLB miss exceptions, which must be handled by software.
Before invalidating an MMU page, it must first be loaded into the UTLB to ensure that
the hardware invalidation is propagated within the coherency domain. It is not sufficient
to simply invalidate the page in memory, since other processors in the coherency
domain can have this particular entry stored in their TLBs.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module