MicroBlaze Processor Reference Guide 59
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Real Mode
The processor references memory when it fetches an instruction and when it accesses data
with a load or store instruction. Programs reference memory locations using a 32-bit
effective address calculated by the processor. When real mode is enabled, the physical
address is identical to the effective address and the processor uses it to access physical
memory. After a processor reset, the processor operates in real mode. Real mode can also
be enabled by clearing the VM bit in the MSR.
Physical-memory data accesses (loads and stores) are performed in real mode using the
effective address. Real mode does not provide system software with virtual address
translation, but the full memory access-protection is available, implemented when
C_USE_MMU > 1 (User Mode) and C_AREA_OPTIMIZED = 0 (Performance) or 2 (Frequency).
Implementation of a real-mode memory manager is more straightforward than a virtual-
mode memory manager. Real mode is often an appropriate solution for memory
management in simple embedded environments, when access-protection is necessary, but
virtual address translation is not required.
Virtual Mode
In virtual mode, the processor translates an effective address into a physical address using
the process shown in
Figure 2-18. With the Physical Address Extension (PAE) the physical
address can be extended up to 64 bits. Virtual mode can be enabled by setting the VM bit
in the MSR.
X-Ref Target - Figure 2-18
Figure 2-18: Virtual-Mode Address Translation
31
24
Processor ID Register
31
n
32-bit Effective Address
0
Effective Page Number
Offset
39
n+8
40-bit Virtual Address
8
Effective Page Number
OffsetPID
0
Translation Look-Aside
Buffer (TLB) Look-Up
31
32-bit Physical Address
0
Real Page Number Offset
32-63
Up to 64-bit Physical Address
0
Physical Address Extension: Real Page Number
Offset
or
0
X19755-091317
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