Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 164
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
Lockstep Interface Description
The lockstep interface on MicroBlaze is designed to connect a master and one or more slave
MicroBlaze instances. The lockstep signals on MicroBlaze are listed in the following table.
The comparison signals provided by Lockstep_Out are listed in the following table.
Table 3-13: MicroBlaze Lockstep Signals
Signal Name Description VHDL Type Direction
Lockstep_Master_Out
Output with signals going from master to
slave MicroBlaze. Not connected on slaves.
std_logic output
Lockstep_Slave_In
Input with signals coming from master to
slave MicroBlaze. Not connected on
master.
std_logic input
Lockstep_Out
Output with all comparison signals from
both master and slaves.
std_logic output
Table 3-14: MicroBlaze Lockstep Comparison Signals
Signal Name Bus Index Range VHDL Type
MB_Halted 0 std_logic
MB_Error 1 std_logic
IFetch 2 std_logic
I_AS 3 std_logic
Instr_Addr 4 to 67 std_logic_vector
Data_Addr 68 to 131 std_logic_vector
Data_Write 132 to 163 std_logic_vector
D_AS 196 std_logic
Read_Strobe 197 std_logic
Write_Strobe 198 std_logic
Byte_Enable 199 to 202 std_logic_vector
M_AXI_IP_AWID 207 std_logic
M_AXI_IP_AWADDR 208 to 271 std_logic_vector
M_AXI_IP_AWLEN 272 to 279 std_logic_vector
M_AXI_IP_AWSIZE 280 to 282 std_logic_vector
M_AXI_IP_AWBURST 283 to 284 std_logic_vector
M_AXI_IP_AWLOCK 285 std_logic
M_AXI_IP_AWCACHE 286 to 289 std_logic_vector
M_AXI_IP_AWPROT 290 to 292 std_logic_vector
M_AXI_IP_AWQOS 293 to 296 std_logic_vector
M_AXI_IP_AWVALID 297 std_logic
M_AXI_IP_WDATA 298 to 329 std_logic_vector
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module