Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 165
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
M_AXI_IP_WSTRB 362 to 365 std_logic_vector
M_AXI_IP_WLAST 370 std_logic
M_AXI_IP_WVALID 371 std_logic
M_AXI_IP_BREADY 372 std_logic
M_AXI_IP_ARID 373 std_logic
M_AXI_IP_ARADDR 374 to 437 std_logic_vector
M_AXI_IP_ARLEN 438 to 445 std_logic_vector
M_AXI_IP_ARSIZE 446 to 448 std_logic_vector
M_AXI_IP_ARBURST 449 to 450 std_logic_vector
M_AXI_IP_ARLOCK 451 std_logic
M_AXI_IP_ARCACHE 452 to 455 std_logic_vector
M_AXI_IP_ARPROT 456 to 458 std_logic_vector
M_AXI_IP_ARQOS 459 to 462 std_logic_vector
M_AXI_IP_ARVALID 463 std_logic
M_AXI_IP_RREADY 464 std_logic
M_AXI_DP_AWID 465 std_logic
M_AXI_DP_AWADDR 466 to 529 std_logic_vector
M_AXI_DP_AWLEN 530 to 537 std_logic_vector
M_AXI_DP_AWSIZE 538 to 540 std_logic_vector
M_AXI_DP_AWBURST 541 to 542 std_logic_vector
M_AXI_DP_AWLOCK 543 std_logic
M_AXI_DP_AWCACHE 544 to 547 std_logic_vector
M_AXI_DP_AWPROT 548 to 550 std_logic_vector
M_AXI_DP_AWQOS 551 to 554 std_logic_vector
M_AXI_DP_AWVALID 555 std_logic
M_AXI_DP_WDATA 556 to 587 std_logic_vector
M_AXI_DP_WSTRB 620 to 623 std_logic_vector
M_AXI_DP_WLAST 628 std_logic
M_AXI_DP_WVALID 629 std_logic
M_AXI_DP_BREADY 630 std_logic
M_AXI_DP_ARID 631 std_logic
M_AXI_DP_ARADDR 632 to 695 std_logic_vector
M_AXI_DP_ARLEN 696 to 703 std_logic_vector
M_AXI_DP_ARSIZE 704 to 706 std_logic_vector
M_AXI_DP_ARBURST 707 to 708 std_logic_vector
M_AXI_DP_ARLOCK 709 std_logic
M_AXI_DP_ARCACHE 710 to 713 std_logic_vector
M_AXI_DP_ARPROT 714 to 716 std_logic_vector
M_AXI_DP_ARQOS 717 to 720 std_logic_vector
Table 3-14: MicroBlaze Lockstep Comparison Signals (Cont’d)
Signal Name Bus Index Range VHDL Type
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module