Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 192
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 4: MicroBlaze Application Binary Interface
Interrupt, Break and Exception Handling
MicroBlaze assumes certain address locations for handling interrupts and exceptions as
indicated in the following table. At these locations, code is written to jump to the
appropriate handlers.
The code expected at these locations is as shown below. The crt0.o initialization file is
passed by the mb-gcc compiler to the mb-ld linker for linking. This file sets the
appropriate addresses of the exception handlers.
The following is code for passing control to Exception, Break and Interrupt handlers,
assuming the default
C_BASE_VECTORS value of 0x00000000:
0x00: bri _start1
0x04: nop
0x08: imm high bits of address (user exception handler)
0x0c: bri _exception_handler
0x10: imm high bits of address (interrupt handler)
0x14: bri _interrupt_handler
0x18: imm high bits of address (break handler)
0x1c: bri low bits of address (break handler)
0x20: imm high bits of address (HW exception handler
0x24: bri _hw_exception_handler
With low-latency interrupt mode, control is directly passed to the interrupt handler for each
individual interrupt utilizing this mode. In this case, it is the responsibility of each handler
to save and restore used registers. The MicroBlaze C compiler (mb-gcc) attribute
fast_interrupt is available to allow this task to be performed by the compiler:
void interrupt_handler_name() __attribute__((fast_interrupt));
Table 4-4: Interrupt and Exception Handling
On Hardware jumps to Software Labels
Start / Reset C_BASE_VECTORS + 0x0 _start
User exception C_BASE_VECTORS + 0x8 _exception_handler
Interrupt C_BASE_VECTORS + 0x10
1
1. With low-latency interrupt mode, the vector address is supplied by the Interrupt Controller.
_interrupt_handler
Break (HW/SW) C_BASE_VECTORS + 0x18 -
Hardware exception C_BASE_VECTORS + 0x20 _hw_exception_handler
Reserved by Xilinx C_BASE_VECTORS + 0x28 -
C_BASE_VECTORS
+ 0x4F
-
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module