Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 97
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Performance Monitoring
With extended debugging, MicroBlaze provides performance monitoring counters to count
various events and to measure latency during program execution. The number of event
counters and latency counters can be configured with
C_DEBUG_EVENT_COUNTERS and
C_DEBUG_LATENCY_COUNTERS respectively, and the counter width can be set to 32, 48 or 64
bits with
C_DEBUG_COUNTER_WIDTH. With the default configuration, the counter width is set
to 32 bits and there are five event counters and one latency counter.
An event counter simply counts the number of times a certain event has occurred, whereas
a latency counter provides the following information:
• Number of times the event has occurred (N)
• The sum of each event latency measured by counting clock cycles from the event starts
until it finishes (ΣL), used to calculate the mean latency
• The sum of each event latency squared (ΣL
2
), used to calculate the latency standard
deviation
• The minimum, shortest, measured latency for all events (L
min
)
• The maximum, longest, measured latency for all events (L
max
)
The mean latency (μ) is calculated by the formula:
The standard deviation (σ) of the latency is calculated by the formula:
Counting can be started or stopped using the Performance Counter Command Register or
by cross trigger events (see
Table 2-62).
When configuring, reading or writing counters, they are accessed sequentially through the
performance counter registers. After every access the selected counter item is incremented.
All counters are sampled simultaneously for reading using the Performance Counter
Command Register. This can be done while counting, or after counting has been stopped.
When an event counter reaches its maximum value, the overflow status bit is set, and the
external interrupt signal
Dbg_Intr is set to one. The interrupt signal is reset to zero by
clearing the counters using the Performance Counter Command Register.
By using one of the event counters to count number of clock cycles, and initializing this
counter to overflow after a predetermined sampling interval, the external interrupt can be
used to periodically sample the performance counters.
The available events are described in Table 2-41, listed in numerical order.
μ
ΣL
N
-------
=
σ
NΣL
2
ΣL()
2
–
N
-----------------------------------------
=
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module