Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 116
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Table 2-62: MicroBlaze Cross Trigger Actions
Number Action Description
0 Debug stop
Stop MicroBlaze if the processor is executing, and set the MB_Halted
output. The same effect is achieved by setting the
Dbg_Stop input.
1 Continue execution
Continue execution if the processor is stopped, and clear the
MB_Halted output.
2 Stop program trace
Stop program trace if tracing is in progress.
3 Start program trace
Start program trace if trace is stopped.
4Stop performance
monitoring
Stop performance monitoring if it is in progress.
5 Start performance
monitoring
Start performance monitoring if it is stopped.
6 Disable profiling
Disable profiling if it is in progress.
7 Enable profiling
Enable profiling if it is disabled.
Table 2-63: MicroBlaze Cross Trigger Events
Number Event Description
0MicroBlaze halted
Generate an event when MicroBlaze is halted. The same event is signaled
when the
MB_Halted output is set.
1Execution resumed
Generate an event when the processor resumes execution from debug
halt. The same event is signaled when the
MB_Halted output is cleared.
2 Program trace
stopped
Generate an event when program trace is stopped by writing a command
to the Program Trace Command Register, when the trace buffer is full, or
by a cross trigger action.
3 Program trace
started
Generate an event when program trace is started by writing a command
to the Program Trace Command Register, by hitting a tracepoint, or by a
cross trigger action.
4Performance
monitoring stopped
Generate an event when performance monitoring is stopped by writing
a command to the Performance Counter Command Register or by a cross
trigger action.
5Performance
monitoring started
Generate an event when performance monitoring is started by writing a
command to the Performance Counter Command Register, or by a cross
trigger action.
6 Profiling disabled
Generate an event when profiling is enabled by writing a command to
the Profiling Control Register or by a cross trigger action.
7 Profiling enabled
Generate an event when profiling is disabled by writing a command to
the Profiling Control Register or by a cross trigger action.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module