Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 115
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Cross Trigger Support
With basic debugging, cross trigger support is provided by two signals, DBG_STOP and
MB_Halted.
• When the DBG_STOP input is set to 1, MicroBlaze will halt after a few instructions. XSDB
will detect that MicroBlaze has halted, and indicate where the halt occurred. The signal
can be used to halt MicroBlaze at any external event, for example when a Vivado®
Integrated Logic Analyzer (ILA) is triggered.
• Whenever MicroBlaze is halted, the
MB_Halted output signal is set to 1; for example
after a breakpoint or watchpoint is hit, after a stop XSDB command, or when the
DBG_STOP input is set. The output is cleared when MicroBlaze execution is resumed by
an XSDB command.
The
MB_Halted signal can be used to trigger a Vivado integrated logic analyzer, or halt
other MicroBlaze cores in a multiprocessor system by connecting the signal to their
DBG_STOP inputs.
With extended debugging, cross trigger support is available in conjunction with the MDM.
The MDM provides programmable cross triggering between all connected processors, as
well as external trigger inputs and outputs. For details, see the MicroBlaze Debug Module
(MDM) Product Guide (PG115)
[Ref 4].
MicroBlaze can handle up to eight cross trigger actions. Cross trigger actions are generated
by the corresponding MDM cross trigger outputs, connected using the Debug bus. The
effect of each of the cross trigger actions is listed in
Table 2-62.
MicroBlaze can generate up to eight cross trigger events. Cross trigger events affect the
corresponding MDM cross trigger inputs, connected using the Debug bus. The cross trigger
events are described in
Table 2-63.
Table 2-61: Profiling Data Write Register (PDWR)
Bits Name Description Reset Value
31:0 Write Data
Data to write to a bin.
0
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module