Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 306
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Appendix A: Performance and Resource Utilization
Resource Utilization
The MicroBlaze core resource utilization for various parameter configurations are measured
for the following devices:
•Virtex-7 (Table A-2)
•Kintex-7 (Table A-3)
•Artix-7 (Table A-4)
• Zynq-7000 (Table A-5)
•Spartan-7 (Table A-6)
•Virtex UltraScale (Table A-7)
• Kintex UltraScale (Table A-8)
•Virtex UltraScale+ (Table A-9)
• Kintex UltraScale+ (Table A-10)
•Zynq UltraScale+ (Table A-11)
The parameter values for each of the measured configurations are shown in Table A-12. The
configurations directly correspond to the predefined presets and templates in the
MicroBlaze Configuration Wizard.
Table A-2: Device Utilization - Virtex-7 FPGAs (XC7VX485T ffg1761-3)
Configuration
Device Resources
LUTs FFs
F
max
(MHz)
Microcontroller Preset 1180 818 308
Real-time Preset 2445 2112 248
Application Preset 4365 3752 211
Minimum Area 633 234 400
Maximum Performance 4111 3195 215
Maximum Frequency 1118 554 400
Linux with MMU 3508 3112 213
Low-end Linux with MMU 3056 2494 215
Typical 2039 1672 256
Frequency Optimized 5890 5772 236
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module