Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 307
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Appendix A: Performance and Resource Utilization
Table A-3: Device Utilization - Kintex-7 FPGAs (XC7K325T ffg900-3)
Configuration
Device Resources
LUTs FFs
F
max
(MHz)
Microcontroller Preset 1174 813 316
Real-time Preset 2472 2112 239
Application Preset 4346 3731 211
Minimum Area 633 230 395
Maximum Performance 4149 3195 223
Maximum Frequency 1127 555 395
Linux with MMU 3508 3130 213
Low-end Linux with MMU 3045 2515 210
Typical 2038 1672 261
Frequency Optimized 5906 5769 254
Table A-4: Device Utilization - Artix-7 FPGAs (XC7A200T fbg676-3)
Configuration
Device Resources
LUTs FFs
F
max
(MHz)
Microcontroller Preset 1174 813 229
Real-time Preset 2452 2112 186
Application Preset 4327 3731 146
Minimum Area 631 230 268
Maximum Performance 4095 3195 162
Maximum Frequency 1102 553 268
Linux with MMU 3509 3111 147
Low-end Linux with MMU 3042 2493 148
Typical 2050 1672 192
Frequency Optimized 5855 5769 167
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module