Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 308
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Appendix A: Performance and Resource Utilization
Table A-5: Device Utilization - Zynq-7000 FPGAs (XC7Z020 clg484-3)
Configuration
Device Resources
LUTs FFs
F
max
(MHz)
Microcontroller Preset 1178 813 213
Real-time Preset 2445 2112 178
Application Preset 4342 3729 148
Minimum Area 634 230 260
Maximum Performance 4094 3195 157
Maximum Frequency 1101 553 260
Linux with MMU 3509 3111 152
Low-end Linux with MMU 3048 2502 158
Typical 2071 1672 188
Frequency Optimized 5850 5762 168
Table A-6: Device Utilization - Spartan-7 FPGAs (XC7S25 csga225-2)
Configuration
Device Resources
LUTs FFs
F
max
(MHz)
Microcontroller Preset 1181 813 194
Real-time Preset 2451 2114 159
Application Preset 4332 3737 131
Minimum Area 629 227 232
Maximum Performance 4092 3195 141
Maximum Frequency 1101 553 232
Linux with MMU 3513 3112 137
Low-end Linux with MMU 3040 2496 137
Typical 2058 1672 168
Frequency Optimized 5828 5748 142
Send Feedback

Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module