Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 120
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Memory Management Unit Protection
To protect the block RAM in the MMU Unified Translation Look-Aside Buffer (UTLB), parity
is used. When a parity error is detected during an address translation, a TLB miss exception
occurs, forcing software to reload the entry.
When a new TLB entry is written using the TLBHI and TLBLO registers, parity is calculated.
One parity bit is used for each entry.
Parity is also checked when a UTLB entry is read using the TLBHI and TLBLO registers. When
a parity error is detected in this case, the entry is marked invalid by clearing the valid bit.
Enabling fault tolerance does not increase the MMU block RAM size, since a spare bit is
available for the parity.
Branch Target Cache Protection
To protect block RAM in the Branch Target Cache, parity is used. When a parity error is
detected when looking up a branch target address, the address is ignored, forcing a normal
branch.
When a new branch address is written to the Branch Target Cache, parity is calculated. One
parity bit is used for each address.
Enabling fault tolerance does not increase the Branch Target Cache block RAM size, since a
spare bit is available for the parity.
Exception Handling
With fault tolerance enabled, if an error occurs in LMB block RAM, the LMB BRAM Interface
Controller generates error signals on the LMB interface.
If exceptions are enabled in the MicroBlaze processor by setting the EE bit in the Machine
Status Register, the uncorrectable error signal either generates an instruction bus exception
or a data bus exception, depending on the affected interface.
Should a bus exception occur when an exception is in progress, MicroBlaze is halted, and
the external error signal
MB_Error is set. This behavior ensures that it is impossible to
execute an instruction corrupted by an uncorrectable error.
Software Support
Scrubbing
To ensure that bit errors are not accumulated in block RAMs, they must be periodically
scrubbed.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module