Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 121
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
The standalone BSP provides the function microblaze_scrub() to perform scrubbing of
the entire LMB block RAM and all MicroBlaze internal block RAMs used in a particular
configuration. This function is intended to be called periodically from a timer interrupt
routine. One location of each block RAM is scrubbed every time it is called, using persistent
data to track the current locations.
The following example code illustrates how this can be done.
#include "xparameters.h"
#include "xtmrctr.h"
#include "xintc.h"
#include "mb_interface.h"
#define SCRUB_PERIOD ...
XIntc InterruptController; /* The Interrupt Controller instance */
XTmrCtr TimerCounterInst;/* The Timer Counter instance */
void MicroBlazeScrubHandler(void *CallBackRef, u8 TmrCtrNumber)
{
/* Perform other timer interrupt processing here */
microblaze_scrub();
}
int main (void)
{
int Status;
/*
* Initialize the timer counter so that it's ready to use,
* specify the device ID that is generated in xparameters.h
*/
Status = XTmrCtr_Initialize(&TimerCounterInst, TMRCTR_DEVICE_ID);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect the timer counter to the interrupt subsystem such that
* interrupts can occur.
*/
Status = XIntc_Initialize(&InterruptController, INTC_DEVICE_ID);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Connect a device driver handler that will be called when an
* interrupt for the device occurs, the device driver handler performs
* the specific interrupt processing for the device
*/
Status = XIntc_Connect(&InterruptController, TMRCTR_DEVICE_ID,
(XInterruptHandler)XTmrCtr_InterruptHandler,
(void *) &TimerCounterInst);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module