Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 90
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Floating-Point Unit (FPU)
Overview
The MicroBlaze floating-point unit is based on the IEEE 754-1985 standard[Ref 18]:
• Uses IEEE 754 single precision floating-point format, including definitions for infinity,
not-a-number (NaN), and zero
• Supports addition, subtraction, multiplication, division, comparison, conversion and
square root instructions
• Implements round-to-nearest mode
• Generates sticky status bits for: underflow, overflow, divide-by-zero and invalid
operation
For improved performance, the following non-standard simplifications are made:
• Denormalized
(1)
operands are not supported. A hardware floating-point operation on a
denormalized number returns a quiet NaN and sets the sticky denormalized operand
error bit in FSR; see Floating-Point Status Register (FSR).
• A denormalized result is stored as a signed 0 with the underflow bit set in FSR. This
method is commonly referred to as Flush-to-Zero (FTZ)
• An operation on a quiet NaN returns the fixed NaN: 0xFFC00000, rather than one of the
NaN operands
• Overflow as a result of a floating-point operation always returns signed ∞
Format
An IEEE 754 single precision floating-point number is composed of the following three
fields:
1. 1-bit sign
2. 8-bit biased exponent
3. 23-bit fraction (a.k.a. mantissa or significand)
The fields are stored in a 32 bit word as defined in the following figure:
1. Numbers that are so close to 0, that they cannot be represented with full precision, that is, any number n that falls in the
following ranges: ( 1.17549*10
-38
> n > 0 ), or ( 0 > n > -1.17549 * 10
-38
)
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module