Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 132
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Data and Instruction Address Extension
MicroBlaze has the ability to address up to 16EB of data controlled by the parameter
C_ADDR_SIZE, and also supports a physical instruction address up to 16EB when the MMU
Physical Address Extension (PAE) is enabled by setting
C_USE_MMU = 3 (Virtual).
The parameter C_ADDR_SIZE can be set to the following values:
There are a number of software limitations with extended addressing:
• The GNU tools only generate ELF files with 32-bit addresses, which means that program
instruction and data memory must be located in the first 4GB of the address space. This
is also the reason the instruction address space does not provide an extended address
unless PAE is enabled.
With PAE enabled, the majority of the program instruction and data can be located at
any physical address, but all software running in real mode must be located in the first
4GB of the address space. The MMU UTLB must also be initialized to set up the virtual
to physical address translation by software running in real mode, before virtual mode is
activated.
• Because all software drivers use address pointers that are 32-bit unsigned integers, it is
not possible to access physical extended addresses above 4GB without modifying the
driver code, and consequently all AXI peripherals should be located in the first 4GB of
the address space.
With PAE enabled, AXI peripherals can be located at any physical address, provided that
the virtual address remains in the first 4GB of the address space.
• The extended address is only treated as a physical address, and the MMU cannot be
used to translate from an extended virtual address to a physical address.
This also means that without PAE support, Linux can only use the data address extension
through a dedicated driver operating in real mode.
°
NONE 4 * 1024
3
bytes 32-bit address, no extended address instructions or PAE
°
64GB 64 * 1024
3
bytes 36-bit address
°
1TB 1024
4
bytes 40-bit address
°
16TB 16 * 1024
4
bytes 44-bit address
°
256TB 256 * 1024
4
bytes 48-bit address
°
4PB 4 * 1024
5
bytes 52-bit address
°
16EB 16 * 1024
6
bytes 64-bit address
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module