Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 305
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Appendix A
Performance and Resource Utilization
Performance
Performance characterization of this core has been done using the margin system
methodology. The details of the margin system characterization methodology is described
in
“IP Characterization and fMAX Margin System Methodology” below.
Maximum Frequencies
The maximum frequencies for the MicroBlaze™ core are provided in Table A-1. The fastest
speed grade of each family is used to generate the results in this table.
Table A-1: Maximum Frequencies
Family F
max
(MHz)
Virtex®-7 393
Kintex®-7 399
Artix-7 260
Zynq
®-7000 272
Spartan
®-7 232
Virtex UltraScale™ 454
Kintex UltraScale 475
Virtex UltraScale+™ 711
Kintex UltraScale+ 724
Zynq UltraScale+ 670
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module