Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 12
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Instructions
Instruction Summary
All MicroBlaze instructions are 32 bits and are defined as either Type A or Type B. Type A
instructions have up to two source register operands and one destination register operand.
Type B instructions have one source register and a 16-bit immediate operand (which can be
extended to 32 bits by preceding the Type B instruction with an imm instruction).
Type B instructions have a single destination register operand. Instructions are provided in
the following functional categories: arithmetic, logical, branch, load/store, and special. The
following table describes the instruction set nomenclature used in the semantics of each
instruction.
Table 2-5 lists the MicroBlaze instruction set. See Chapter 5, MicroBlaze
Instruction Set Architecture, for more information on these instructions.
Table 2-5: Instruction Set Nomenclature
Symbol Description
Ra R0 - R31, General Purpose Register, source operand a
Rb R0 - R31, General Purpose Register, source operand b
Rd R0 - R31, General Purpose Register, destination operand
SPR[x] Special Purpose Register number x
MSR Machine Status Register = SPR[1]
ESR Exception Status Register = SPR[5]
EAR Exception Address Register = SPR[3]
FSR Floating-point Unit Status Register = SPR[7]
PVRx Processor Version Register, where x is the register number = SPR[8192 + x]
BTR Branch Target Register = SPR[11]
PC Execute stage Program Counter = SPR[0]
x[y] Bit y of register x
x[y:z] Bit range y to z of register x
x Bit inverted value of register x
Imm 16 bit immediate value
Immx x bit immediate value
FSLx 4 bit AXI4-Stream port designator, where x is the port number
C Carry flag, MSR[29]
Sa Special Purpose Register, source operand
Sd Special Purpose Register, destination operand
s(x) Sign extend argument x to 32-bit value
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module