Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 6
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 1
Introduction
The MicroBlaze™ Processor Reference Guide provides information about the 32-bit soft
processor, MicroBlaze, which is included in Vivado. The document is intended as a guide to
the MicroBlaze hardware architecture.
Guide Contents
This guide contains the following chapters:
• Chapter 2, MicroBlaze Architecture contains an overview of MicroBlaze features as well
as information on Big-Endian and Little-Endian bit-reversed format, 32-bit general
purpose registers, cache software support, and AXI4-Stream interfaces.
• Chapter 3, MicroBlaze Signal Interface Description describes the types of signal
interfaces that can be used to connect MicroBlaze.
• Chapter 4, MicroBlaze Application Binary Interface describes the Application Binary
Interface important for developing software in assembly language for the processor.
• Chapter 5, MicroBlaze Instruction Set Architecture provides notation, formats, and
instructions for the Instruction Set Architecture (ISA) of MicroBlaze.
• Appendix A, Performance and Resource Utilization contains maximum frequencies and
resource utilization numbers for different configurations and devices.
• Appendix B, Additional Resources and Legal Notices provides links to documentation
and additional resources.
Send Feedback

Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module