Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 174
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
MicroBlaze Core Configurability
The MicroBlaze core has been developed to support a high degree of user configurability.
This allows tailoring of the processor to meet specific cost/performance requirements.
Configuration is done using parameters that typically enable, size, or select certain
processor features. For example, the instruction cache is enabled by setting the
C_USE_ICACHE parameter. The size of the instruction cache, and the cacheable memory
range, are all configurable using:
C_CACHE_BYTE_SIZE, C_ICACHE_BASEADDR, and
C_ICACHE_HIGHADDR respectively.
Parameters valid for the latest version of MicroBlaze are listed in Table 3-19. Not all of these
are recognized by older versions of MicroBlaze; however, the configurability is fully
backward compatible.
Note: Shaded rows indicate that the parameter has a fixed value and cannot be modified.
Table 3-19: Configuration Parameters
Parameter Name Feature/Description
Allowable
Values
Default
Value
Tool
Assigned
VHDL Type
C_FAMILY Target Family
Listed in
Table 3-20
virtex7
yes string
C_DATA_SIZE Data Size 32 32 NA integer
C_ADDR_SIZE Address Size 32-64 32 NA integer
C_DYNAMIC_BUS_SIZING Legacy 1 1 NA integer
C_SCO Xilinx internal 0 0 NA integer
C_AREA_OPTIMIZED Select implementation
optimization:
0 = Performance
1 = Area
2 = Frequency
0, 1, 2 0 integer
C_OPTIMIZATION Reserved for future use 0 0 NA integer
C_INTERCONNECT Select interconnect
2 = AXI4 only
3 = AXI4 and ACE
2, 3 2 integer
C_ENDIANNESS Select endianness
1 = Little Endian
1 1 yes integer
C_BASE_VECTORS
1
Configurable base
vectors
0x00000000
-0xffffff80
0x0000
0000
std_logic_
vector
C_FAULT_TOLERANT Implement fault
tolerance
0, 1 0
yes integer
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module