Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 175
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
C_ECC_USE_CE_EXCEPTION Generate exception for
correctable ECC error
0,1 0
integer
C_LOCKSTEP_SLAVE Lockstep Slave 0, 1 0 integer
C_AVOID_PRIMITIVES Disallow FPGA
primitives
0 = None
1 = SRL
2 = LUTRAM
3 = Both
0, 1, 2, 3 0
integer
C_ENABLE_DISCRETE_PORTS Show discrete ports 0, 1 0 integer
C_PVR Processor version
register mode selection
0 = None
1 = Basic
2 = Full
0, 1, 2 0
integer
C_PVR_USER1 Processor version
register USER1 constant
0x00-0xff 0x00
std_logic_
vector
(0 to 7)
C_PVR_USER2 Processor version
register USER2 constant
0x00000000
-0xffffffff
0x0000
0000
std_logic_
vector
(0 to 31)
C_RESET_MSR_IE
C_RESET_MSR_BIP
C_RESET_MSR_ICE
C_RESET_MSR_DCE
C_RESET_MSR_EE
C_RESET_MSR_EIP
Reset value for MSR
register bits IE, BIP, ICE,
DCE, EE, and EIP
Any
combination
of the
individual
bits
0x0000
std_logic
C_INSTANCE Instance Name Any
instance
name
micro
blaze
yes
string
C_D_AXI Data side AXI interface 0, 1 0 integer
C_D_LMB Data side LMB interface 0, 1 1 integer
C_I_AXI Instruction side AXI
interface
0, 1 0
integer
C_I_LMB Instruction side LMB
interface
0, 1 1
integer
C_USE_BARREL Include barrel shifter 0, 1 0 integer
Table 3-19: Configuration Parameters (Cont’d)
Parameter Name Feature/Description
Allowable
Values
Default
Value
Tool
Assigned
VHDL Type
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module