Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 176
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
C_USE_DIV Include hardware
divider
0, 1 0
integer
C_USE_HW_MUL Include hardware
multiplier
0 = None
1 = Mul32
2 = Mul64
0, 1, 2 1
integer
C_USE_FPU Include hardware
floating-point unit
0 = None
1 = Basic
2 = Extended
0, 1, 2 0
integer
C_USE_MSR_INSTR Enable use of
instructions: MSRSET
and MSRCLR
0, 1 1
integer
C_USE_PCMP_INSTR Enable use of
instructions: CLZ,
PCMPBF, PCMPEQ, and
PCMPNE
0, 1 1
integer
C_USE_REORDER_INSTR Enable use of
instructions: Reverse
load, reverse store, and
swap
0, 1 1
integer
C_UNALIGNED_EXCEPTIONS Enable exception
handling for unaligned
data accesses
0, 1 0
integer
C_ILL_OPCODE_EXCEPTION Enable exception
handling for illegal op-
code
0, 1 0
integer
C_M_AXI_I_BUS_EXCEPTION Enable exception
handling for M_AXI_I
bus error
0, 1 0
integer
C_M_AXI_D_BUS_EXCEPTION Enable exception
handling for M_AXI_D
bus error
0, 1 0
integer
C_DIV_ZERO_EXCEPTION Enable exception
handling for division by
zero or division
overflow
0, 1 0
integer
Table 3-19: Configuration Parameters (Cont’d)
Parameter Name Feature/Description
Allowable
Values
Default
Value
Tool
Assigned
VHDL Type
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module