Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 177
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
C_FPU_EXCEPTION Enable exception
handling for hardware
floating-point unit
exceptions
0, 1 0
integer
C_OPCODE_0x0_ILLEGAL Detect opcode 0x0 as an
illegal instruction
0,1 0
integer
C_FSL_EXCEPTION Enable exception
handling for Stream
Links
0,1 0
integer
C_ECC_USE_CE_EXCEPTION Generate Bus Error
Exceptions for
correctable errors
0,1 0
integer
C_USE_STACK_PROTECTION Generate exception for
stack overflow or stack
underflow
0,1 0
integer
C_IMPRECISE_EXCEPTIONS Allow imprecise
exceptions for ECC
errors in LMB memory
0,1 0
integer
C_DEBUG_ENABLED MDM Debug interface
0 = None
1 = Basic
2 = Extended
0,1,2 1
integer
C_NUMBER_OF_PC_BRK Number of hardware
breakpoints
0-8 1 integer
C_NUMBER_OF_RD_ADDR_BRK Number of read address
watchpoints
0-4 0 integer
C_NUMBER_OF_WR_ADDR_BRK Number of write
address watchpoints
0-4 0 integer
C_DEBUG_EVENT_COUNTERS Number of Performance
Monitor event counters
0-48 5 integer
C_DEBUG_LATENCY_COUNTERS Number of Performance
Monitor latency
counters
0-7 1 integer
C_DEBUG_COUNTER_WIDTH Performance Monitor
counter width
32,48,64 32 integer
Table 3-19: Configuration Parameters (Cont’d)
Parameter Name Feature/Description
Allowable
Values
Default
Value
Tool
Assigned
VHDL Type
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module