Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 178
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
C_DEBUG_TRACE_SIZE Trace Buffer size
Embedded: 0, ≥ 8192
External: 0, 32 - 8192
0, 32, 64,
128, 256,
8192,
16384,
32768,
65536,
131072
8192 integer
C_DEBUG_PROFILE_SIZE Profile Buffer size 0, 4096,
8192,
16384,
32768,
65536,
131072
0 integer
C_DEBUG_EXTERNAL_TRACE External Program Trace 0,1 0
yes
integer
C_DEBUG_INTERFACE Debug Interface:
0 = Debug Serial
1 = Debug Parallel
2 = AXI4-Lite
0,1,2 0 integer
C_ASYNC_INTERRUPT Asynchronous Interrupt 0,1 0
yes
integer
C_ASYNC_WAKEUP Asynchronous Wakeup 00,01,10,11 00
yes
integer
C_INTERRUPT_IS_EDGE Level/Edge Interrupt 0, 1 0
yes
integer
C_EDGE_IS_POSITIVE Negative/Positive Edge
Interrupt
0, 1 1 yes
integer
C_FSL_LINKS Number of AXI-Stream
interfaces
0-16 0
integer
C_USE_EXTENDED_FSL_INSTR Enable use of extended
stream instructions
0, 1 0
integer
C_ICACHE_BASEADDR Instruction cache base
address
0x0 -
0xFFFFFFFF
FFFFFFFF
0x0
std_logic_
vector
C_ICACHE_HIGHADDR Instruction cache high
address
0x0 -
0xFFFFFFFF
FFFFFFFF
0x3FFFF
FFF
std_logic_
vector
C_USE_ICACHE Instruction cache 0, 1 0 integer
C_ALLOW_ICACHE_WR Instruction cache write
enable
0, 1 1
integer
C_ICACHE_LINE_LEN Instruction cache line
length
4, 8, 16 4
integer
Table 3-19: Configuration Parameters (Cont’d)
Parameter Name Feature/Description
Allowable
Values
Default
Value
Tool
Assigned
VHDL Type
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module