Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 149
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 3: MicroBlaze Signal Interface Description
AXI4 and ACE Interface Description
Memory Mapped Interfaces
Peripheral Interfaces
The MicroBlaze AXI4 memory mapped peripheral interfaces are implemented as 32-bit
masters. Each of these interfaces only have a single outstanding transaction at any time,
and all transactions are completed in order.
• The instruction peripheral interface (M_AXI_IP) only performs single word read
accesses, and is always set to use the AXI4-Lite subset.
• The data peripheral interface (
M_AXI_DP) performs single word accesses, and is set to
use the AXI4-Lite subset as default, but is set to use AXI4 when enabling exclusive
access for LWX and SWX instructions. Halfword and byte writes are performed by
setting the appropriate byte strobes.
The instruction peripheral interface (M_AXI_IP) address width can range from 32 - 64 bits
when the MMU physical address extension (PAE) is enabled, depending on the value of the
parameter C_ADDR_SIZE.
The data peripheral interface (M_AXI_DP) address width can range from 32 - 64 bits,
depending on the value of the parameter C_ADDR_SIZE.
Cache Interfaces
The AXI4 memory mapped cache interfaces are implemented either as 32-bit, 128-bit, 256-
bit, or 512-bit masters, depending on cache line length and data width parameters, whereas
the AXI Coherency Extension (ACE) interfaces are implemented as 32-bit masters.
• With a 32-bit master, the instruction cache interface (M_AXI_IC or M_ACE_IC) performs
4 word, 8 word or 16 word burst read accesses, depending on cache line length. With
128-bit, 256-bit, or 512-bit masters, only single read accesses are performed.
With a 32-bit master, this interface can have multiple outstanding transactions, issuing
up to 2 transactions or up to 5 transactions when stream cache is enabled. The stream
cache can request two cache lines in advance, which means that in some cases 5
outstanding transactions can occur. In this case the number of outstanding reads is set
to 8, since this must be a power of two. With 128-bit, 256-bit, or 512-bit masters, the
interface only has a single outstanding transaction.
How memory locations are accessed depend on parameter C_ICACHE_ALWAYS_USED.
If the parameter is 1, the cached memory range is always accessed using the AXI4 or ACE
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module