Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 313
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Appendix A: Performance and Resource Utilization
IP Characterization and f
MAX
Margin System Methodology
Introduction
This section describes the methods to determine the maximum frequency (F
MAX
) of IP
operation within a system design. The method enables realistic performance reporting for
any Xilinx FPGA architecture. The maximum frequency of a design is the maximum
frequency at which the overall system can be implemented without encountering timing
issues.
C_USE_EXTENDED_FSL_INSTR
0 0 0 0 0 0 0 0 0 0
C_USE_FPU
0 0 1 0 2 0 0 0 0 2
C_USE_HW_MUL
1 1 2 0 2 0 2 1 1 2
C_USE_ICACHE
0 1 1 0 1 0 1 1 1 1
C_USE_MMU
0 0 3 0 0 0 3 3 0 3
C_USE_MSR_INSTR
1 1 1 0 1 0 1 1 1 1
C_USE_PCMP_INSTR
1 1 1 0 1 0 1 1 1 1
C_USE_REORDER_INSTR
0 1 1 0 1 1 1 1 1 1
C_USE_BRANCH_TARGET_CACHE
0 0 0 0 1 0 0 0 0 1
C_BRANCH_TARGET_CACHE_SIZE
0 0 0 0 0 0 0 0 0 0
C_ICACHE_STREAMS
0 0 1 0 1 0 1 0 0 0
C_ICACHE_VICTIMS
0 0 8 0 8 0 8 0 0 0
C_DCACHE_VICTIMS
0 0 0 0 8 0 8 0 0 0
C_ICACHE_FORCE_TAG_LUTRAM
0 0 0 0 0 0 0 0 0 0
C_DCACHE_FORCE_TAG_LUTRAM
0 0 0 0 0 0 0 0 0 0
C_ICACHE_ALWAYS_USED
0 1 1 0 1 0 1 1 0 1
C_DCACHE_ALWAYS_USED
0 1 1 0 1 0 1 1 0 1
C_D_AXI
1 1 1 0 1 0 1 1 0 1
C_USE_INTERRUPT
1 1 1 0 0 0 1 1 0 1
C_USE_STACK_PROTECTION
0 1 0 0 0 0 0 0 0 0
Table A-12: Parameter Configurations (Cont’d)
Parameter
Configuration Parameter Values
Microcontroller
Preset
Real-time
Preset
Application
Preset
Minimum
Area
Maximum
Performance
Maximum
Frequency
Linux
with MMU
Low-end Linux
with MMU
Typical
Frequency
Optimized
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module