Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 314
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Appendix A: Performance and Resource Utilization
The F
MAX
Margin System Methodology
It is important to determine the IP performance in the context of a user system. In the case
of the MicroBlaze characterization, the system includes the following items:
• The IP under test (MicroBlaze Processor)
• Local Memory (LMB)
• One level of Interconnect (AXI4, AXI4-Lite, AXI4-Stream)
• Memory controller (EMC)
• On-chip BRAM controller
• Peripherals (UART, Timer, Interrupt Controller, MDM)
Determining the F
MAX
of an Embedded IP with these components provides a more realistic
performance target.
The system above has three types of AXI Interconnect. AXI4-Lite used for peripheral
command and control, AXI4 used for memory accesses, and AXI4-Stream used for
MicroBlaze streams.
For F
MAX
Margin System Analysis, the clock frequency of the system is incremented up to
the maximum frequency where the system breaks with timing violations (worst case
negative slack). The reported frequency is the failing frequency subtracted with this worst
case negative slack.
Tool Options and Other Factors
Xilinx tools offer a number of options and settings that provide a trade-off between design
performance, resource usage, implementation run time, and memory footprint. The settings
that produce the best results for one design might not necessarily work for another design.
For the purpose of the F
MAX
Margin System Analysis, the IP design is characterized with
default settings without specific constraints (other than the clocking constraint). This
analysis is done with all different FPGA architectures and the maximum speed grade.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module