Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 126
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Lockstep Operation
MicroBlaze is able to operate in a lockstep configuration, where two or more identical
MicroBlaze cores execute the same program. By comparing the outputs of the cores, any
tampering attempts, transient faults or permanent hardware faults can be detected.
System Configuration
The parameter C_LOCKSTEP_SLAVE is set to one on all slave MicroBlaze cores in the system,
except the master (or primary) core. The master core drives all the output signals, and
handles the debug functionality. The port
Lockstep_Master_Out on the master is
connected to the port
Lockstep_Slave_In on the slaves, in order to handle debugging.
The slave cores should not drive any output signals, only receive input signals. This must be
ensured by only connecting signals to the input ports of the slaves. For buses this means
that each individual input port must be explicitly connected.
The port Lockstep_Out on the master and slave cores provide all output signals for
comparison. Unless an error occurs, individual signals from each of the cores are identical
every clock cycle.
To ensure that lockstep operation works properly, all input signals to the cores must be
synchronous. Input signals that could require external synchronization are
Interrupt,
Reset, Ext_Brk, and Ext_Nm_Brk.
Use Cases
Two common use cases are described here. In addition, lockstep operation provides the
basis for implementing triple modular redundancy on MicroBlaze core level.
Tamper Protection
This application represents a high assurance use case, where it is required that the system
is tamper-proof. A typically example is a cryptographic application.
The approach involves having two redundant MicroBlaze processors with dedicated local
memory and redundant comparators, each in a protected area. The outputs from each
processor feed two comparators and each processor receive copies of every input signal.
The redundant MicroBlaze processors are functionally identical and completely
independent of each other, without any connecting signals. The only exception is debug
logic and associated signals, because it is assumed that debugging is disabled before any
productization and certification of the system.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module