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Xilinx MicroBlaze - Page 125

Xilinx MicroBlaze
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MicroBlaze Processor Reference Guide 125
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Full
This system uses all of the features provided by the LMB BRAM Interface Controller, to
enable full error injection capability, as well as error monitoring and interrupt generation. It
is a typical system with Uncorrectable Error First Failing registers and Fault Injection
registers added. All features are switched on for full control of ECC functionality for system
debug or systems with high fault tolerance requirements. Parameters set are:
-
C_ECC = 1
-
C_CE_COUNTER_WIDTH = 10
-
C_ECC_STATUS_REGISTER = 1
-
C_CE_FAILING_REGISTERS = 1
-
C_UE_FAILING_REGISTERS = 1
-
C_FAULT_INJECT = 1
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