Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 125
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Full
This system uses all of the features provided by the LMB BRAM Interface Controller, to
enable full error injection capability, as well as error monitoring and interrupt generation. It
is a typical system with Uncorrectable Error First Failing registers and Fault Injection
registers added. All features are switched on for full control of ECC functionality for system
debug or systems with high fault tolerance requirements. Parameters set are:
-
C_ECC = 1
-
C_CE_COUNTER_WIDTH = 10
-
C_ECC_STATUS_REGISTER = 1
-
C_CE_FAILING_REGISTERS = 1
-
C_UE_FAILING_REGISTERS = 1
-
C_FAULT_INJECT = 1
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module