Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 316
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Appendix B: Additional Resources and Legal Notices
References
The following documents are available using your Vivado® installation.
Relevant individual documents are linked below.
1. PowerPC Processor Reference Guide (UG011)
2. LogiCore IP Soft Error Mitigation Controller Product Guide (PG036)
3. LogiCore IP Processor LMB BRAM Interface Controller Product Guide (PG112)
4. MicroBlaze Debug Module (MDM) Product Guide (PG115)
5. Device Reliability Report User Guide (UG116)
6. LogiCore IP System Cache Product Guide (PG118)
7. Triple Modular Redundancy (TMR) Subsystem Product Guide (PG268)
8. Hierarchical Design Methodology Guide (UG748)
9. Xilinx Software Development Kit Help (UG782)
10. Vivado Design Suite User Guide: Designing With IP (UG896)
11. Vivado Design Suite User Guide: Embedded Processor Hardware Design (UG898)
12. Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)
13. Embedded System Tools Reference Manual (UG1043)
14. AMBA 4 AXI4-Stream Protocol Specification, Version 1.0 (Arm IHI 0051A)
15. AMBA AXI and ACE Protocol Specification (Arm IHI 0022E)
16. LogiCore IP UltraScale Architecture Soft Error Mitigation Controller Product Guide (PG187)
The following lists additional resources you can access directly using the provided URLs.
17. The entire set of GNU manuals: http://www.gnu.org/manual
18. IEEE 754-1985 standard http://en.wikipedia.org/wiki/IEEE_754-1985
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module