Xilinx MicroBlaze Reference Guide

MicroBlaze Processor Reference Guide 81
UG984 (v2018.2) June 21, 2018 www.xilinx.com
Chapter 2: MicroBlaze Architecture
Instruction Cache
Overview
MicroBlaze can be used with an optional instruction cache for improved performance when
executing code that resides outside the LMB address range.
The instruction cache has the following features:
• Direct mapped (1-way associative)
• User selectable cacheable memory address range
• Configurable cache and tag size
• Caching over AXI4 interface (
M_AXI_IC)
• Option to use 4, 8 or 16 word cache-line
• Cache on and off controlled using a bit in the MSR
• Optional WIC instruction to invalidate instruction cache lines
• Optional stream buffers to improve performance by speculatively prefetching
instructions
• Optional victim cache to improve performance by saving evicted cache lines
• Optional parity protection that invalidates cache lines if a Block RAM bit error is
detected
• Optional data width selection to either use 32 bits, an entire cache line, or 512 bits
General Instruction Cache Functionality
When the instruction cache is used, the memory address space is split into two segments:
a cacheable segment and a non-cacheable segment. The cacheable segment is determined
by two parameters:
C_ICACHE_BASEADDR and C_ICACHE_HIGHADDR. All addresses within
this range correspond to the cacheable address segment. All other addresses are non-
cacheable.
The cacheable segment size must be 2
N
, where N is a positive integer. The range specified
by
C_ICACHE_BASEADDR and C_ICACHE_HIGHADDR must comprise a complete power-of-two
range, such that range = 2
N
and the N least significant bits of C_ICACHE_BASEADDR must be
zero.
The cacheable instruction address consists of two parts: the cache address, and the tag
address. The MicroBlaze instruction cache can be configured from 64 bytes to 64 kB. This
corresponds to a cache address of between 6 and 16 bits. The tag address together with the
cache address should match the full address of cacheable memory.
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Xilinx MicroBlaze Specifications

General

Architecture	32-bit RISC
Cache	Configurable Instruction and Data Cache
Category	Soft Processor Core
Data Width	32-bit
Memory Management Unit (MMU)	Optional
Floating Point Unit (FPU)	Optional
Interrupt Controller	Configurable
Memory Management	Optional MMU
Configurability	Highly Configurable
Pipeline Stages	3-stage
FPGA Integration	Xilinx FPGAs
Bus Interface	PLB
Debug Interface	JTAG
Typical Clock Speed	Varies depending on FPGA and configuration (e.g., 100-400+ MHz)
Implementation	Soft core (synthesized logic)
Maximum Performance	Varies with FPGA and configuration
Debug Support	Integrated Debug Module